According to a group of researchers from Vrije Universiteit Amsterdam in the Netherlands, ASLR is fundamentally insecure on modern cache-based architectures, although it is used as the main line of defense against memory corruption attacks. Although existing attacks against ASLR rely on software vulnerabilities or on repeated memory probing, simpler attacks are possible, the researchers claim.
In their paper (PDF), the researchers detail a new EVICT+TIME cache attack on the virtual address translation that the memory management unit (MMU) of modern processors performs. The attack, they explain, “relies on the property that the MMU’s page-table walks result in caching page-table pages in the shared last-level cache (LLC),”
The attack, the researchers explain, relies on the interplay between the MMU and the caches during virtual to physical address translation, a behavior critical to efficient code execution on modern CPUs. The issue, they say, is that modern architectures allow attackers with knowledge to craft memory accesses that manifest timing differences to disclose memory access and infer the bits that make up the address. These timing differences are considered fundamental, reflecting the way caches optimize accesses in the memory hierarchy, the researchers explain.
The AnC attack, the paper says, is applicable to a wide range of modern architectures, including Intel, ARM and AMD, while mitigation without naively disabling caches is hard, because it targets the low-level operations of the MMU. The researchers say that the AnC attack was possible on all of the tested architectures and that all, except for ARMv7, allowed them to fully derandomize ASLR.
The researchers also explain that an on-going AnC attack can be detected using performance counters, although this type of defense is prone to false-positives. Partitioning the shared LLC can also be used, though with performance impact, while reducing the accuracy of the timers to make it harder for attackers to differentiate between cached and memory accesses is often costly to implement. AnC can also be mitigated through caching PT entries in a separate cache rather than the data caches.
“The conclusion is that such caching behavior and strong address space randomization are mutually exclusive. Because of the importance of the caching hierarchy for the overall system performance, all fixes are likely to be too costly to be practical. Moreover, even if mitigations are possible in hardware, such as separate cache for page tables, the problems may well resurface in software. We hence recommend ASLR to no longer be trusted as a first line of defense against memory error attacks and for future defenses not to rely on it as a pivotal building block,” the paper concludes.